As the development of the semiconductor technology, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have their feature sizes being decreased continuously. The decrease in size of the MOSFETs causes a severe problem of gate current leakage. The gate leakage current can be reduced by using a high K gate dielectric layer, which may have an increased physical thickness with respect to a given equivalent oxide thickness (EOT). Unfortunately, a conventional Poly-Si gate is incompatible with the high K gate dielectric layer. By using a combination of a metal gate and the high K gate dielectric layer, it is possible not only to avoid the depletion effect of the Poly-Si gate and decrease gate resistance, but also to avoid boron penetration and enhance device reliability. Therefore, the combination of the metal gate and the high K gate dielectric layer is widely used in the MOSFETs. However, integration of the metal gate and the high K gate dielectric layer is still confronted with many challenges, such as thermal stability and interfacial states. Particularly, due to the Fermi-Pinning Effect, it is difficult for the MOSEFTs using the metal gate and the high K gate dielectric layer to have an adequately low threshold voltage.
To obtain an appropriate threshold voltage, a P type MOSFET should have its effective work function near the bottom of the conduction band of Si (about 5.2 eV). It is desired to select an appropriate combination of a metal gate and a high-K gate dielectric layer for the P type MOSFET, so as to achieve the desired threshold voltage. However, it is difficult to obtain such a high effective work function simply by altering materials.